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Gen-3 Thermal Management Technology: Role of Microchannels and Nanostructures in an Embedded Cooling Paradigm OPEN ACCESS

[+] Author and Article Information
Avram Bar-Cohen

Program Manager
Microsystems Technology Office,
Defense Advanced Research Projects Agency (DARPA),
675 North Randolph Street,
Arlington, VA 22203

Manuscript received October 24, 2012; final manuscript received January 22, 2013; published online July 23, 2013. Assoc. Editor: Debjyoti Banerjee.

J. Nanotechnol. Eng. Med 4(2), 020907 (Jul 23, 2013) (3 pages) Paper No: NANO-12-1130; doi: 10.1115/1.4023898 History: Received October 24, 2012; Revised January 22, 2013

The thermal management challenges facing electronic system developers and the need, as well as challenges, associated with the development of a Gen-3 embedded cooling paradigm are examined. We argue that the inherent limitations of the prevailing “remote cooling” technology have resulted in commercial and military electronic systems that are thermally-limited, performing well below the inherent electrical capability of the device technology they exploit. To overcome these limitations and remove a significant barrier to continued Moore's law progression in electronic components and systems, DARPA is pursuing the aggressive development of thermal management “embedded” in the chip, substrate, and/or package to directly cool the heat generation sites. The options and challenges associated with the development of this “Gen-3” thermal management technology are described.

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The increased integration density of electronic components and subsystems, including the nascent commercialization of 3D chip stack technology, has exacerbated the thermal management challenges facing electronic system developers. The confluence of chip power dissipation above 100 W, localized hot spots with fluxes above 1 kW/cm2, and package-level volumetric heat generation that can exceed 1 kW/cm3 has exposed the limitations of the current “remote cooling” paradigm and its inability to facilitate continued enhancements in the performance of advanced silicon and compound semiconductor components. These thermal limitations have compromised the decades-long Moore's law progression in microprocessor performance and threaten to derail the innovation engine which has been responsible for much of the microelectronic revolution.

In conventional cooling architectures for electronics, reliance on thermal conduction and spreading, in the commonly-used chips and substrates and across the multiple material interfaces present in packages and modules, severely constrains the ability of remotely located heat rejection surfaces to reduce the temperature rise of critical on-chip hot spots and individual chips in a module or in a stack. Moreover, continued application of this “remote cooling” paradigm, has resulted in electronic systems in which the thermal management hardware accounts for a large fraction of the volume, weight, and cost of advanced electronic systems and undermines efforts to transfer emerging electronic components to portable, as well as other small form-factor, applications.

In 2008 DARPA initiated the Thermal Management Technologies (TMT) program to address these thermal management challenges by reducing the overall thermal resistance associated with the prevailing “remote cooling” paradigm, shown in Fig. 1. The TMT program includes several distinct efforts to utilize emerging micro- and nanotechnology for enhanced thermal performance and these efforts are now coming to fruition, with considerable success (see, e.g., Ref. [1]).

The Microtechnologies for Air Cooled Exchangers (MACE) effort seeks to develop heat sinks which utilize flow agitators, synthetic jets, compressed air, and fins with integral heat pipes to reduce the thermal resistivity towards 10 cm2 K/W, meaning a 10 K temperature rise for a heat flux of 1 W/cm2, with a fan coefficient of performance (COP) approaching 30. The thermal ground plane (TGP) thrust is developing high-performance “vapor chamber” heat spreaders in which micro-nano biporous wicks, some with hydrophobic-hydrophilic surfaces and expansion-matched cases, can provide in-plane thermal conductivities between 10 kW/mK and 20 kW/mK, or 25–50 times higher than copper and more than 10 times higher than synthetic diamond. Enhanced thermal interface materials, based on mechanically-compliant laminated solder-graphite, GLAD fabricated copper nanosprings, and arrays of carbon nano tubes (CNTs), respectively, that could accommodate the differential expansion between silicon and copper while reducing the thermal resistivity to below 0.01 cm2 K/W for a 0.1 mm thick layer, are resulting from the Nano Thermal Interfaces (NTI) thrust. Miniature high-efficiency refrigeration systems, based on thermoelectric or Sterling cycle technologies that can be inserted into the chip stack-up and capable of reaching COPs of 2 for a 15 K temperature reduction under an applied heat flux greater than 25 W/cm2, are being pursued under the active cooling module (ACM) effort.

Despite these developments and ongoing evolutionary improvements in COTS thermal packaging technology, the sequential conductive thermal resistances, inherent to the “remote cooling” paradigm, have resulted in only limited improvements in the overall junction-to-ambient thermal resistance of high-performance electronic systems during the past decade. Consequently, many commercial and military electronic systems are thermally-limited, performing well below the inherent electrical capability of the device technology they exploit.

To overcome these limitations and remove a significant barrier to continued Moore's law progression in electronic components and systems, it is essential to “embed” aggressive thermal management in the chip, substrate, and/or package and directly cool the heat generation sites. The development of “Gen-3” thermal management technology, following on the Gen-1 air-conditioning approaches of the early years and the decades-long commitment to the Gen-2 “remote cooling” paradigm, is the focus of the current DARPA Intra/Inter Chip Enhanced Cooling (ICECool) thermal packaging program.

Detailed consideration of power distribution in the chip and package, and how power delivery needs and constraints are integrated into the design, fabrication, and optimization of advanced electronic and photonic components, can inform and guide the articulation of the Gen-3 embedded cooling paradigm [2]. Thus, it is expected that ICECool will involve the creation of a rich micro/nano grid of thermal interconnects, using high thermal conductivity, as well as thermoelectric, materials to link on-chip hot spots to convectively and evaporatively cooled microchannels. Such intra/inter chip enhanced cooling approaches will need to be compatible with the materials, fabrication procedures, and thermal management needs of emerging homogeneous and heterogeneous integration in 3D chip stacks, 2.5D constructs, and planar arrays. A conceptual ICECool device is shown in Fig. 2.

An intrachip approach would involve fabricating micropores and microchannels directly into the chip [3,4], while an interchip approach would involve utilizing the microgap between chips in three-dimensional stacks [5], as the cooling channel. In addition to the inclusion of an appropriate grid of passive and/or active thermal interconnects, it is expected that a combination of intrachip and interchip approaches, linked with thru-silicon and/or “blind” micropores will confer added thermal management functionality. These microchannels and/or micropores will need to be integrated into a fluid distribution network, delivering chilled fluid to the chip or package and extracting a mixture of heated liquid and vapor to be transported to the ambiently cooled radiator. Moreover, on-chip microvalves, thermostatically or digitally controlled, will be needed to regulate the flow of the coolant and assure the most efficient use of its latent and sensible cooling capacity.

Successful development and implementation of this Gen-3 thermal packaging paradigm would place thermal management on an equal footing with functional design and power delivery, transforming electronic system architecture and unleashing the power of nanofeatured device technology, while overcoming the SWaP bottleneck encountered by many advanced electronic systems.

Some 30 years of thermofluid and microfabrication R&D, driven initially by the publication of the Tuckerman and Pease microchannel cooler paper in 1981 [3] and more recently by compact heat exchanger and biofluidic applications, has created the scientific and engineering foundation for the aggressive implementation of the “embedded cooling” paradigm. Nevertheless, substantial development and modeling challenges must be overcome if Gen-3 “embedded cooling” techniques are to supplant the current “remote cooling” paradigm.

The DARPA ICECool program will thus address multiple microfabrication, thermofluid, and design challenges, including

  • Subtractive and additive microfabrication in silicon, silicon carbide, and synthetic diamond of high aspect ratio, thin-walled microchannels and high aspect ratio micropores; low thermal boundary resistance, high thermal conductivity thermal interconnect grids; on-chip, high power factor, high COP thin-film thermoelectric coolers; on-chip microvalves with wide flow rate control; and hermetic attachment of liquid supply and liquid/vapor removal tubes.

  • Convective and evaporative thermofluid transport in microchannels—removal of kW/cm2 heat fluxes with submillimeter 5 kW/cm2 “hot spots”; low pumping power liquid-vapor manifolds, micrcochannels, and micropores; high-exit-quality evaporative flows without flow instabilities and/or local dryout; and high fidelity thermofluid models for single-and two-phase flow in microchannels, microgaps, and micropores.

  • Thermal and electrical codesign which moves progressively from passive, thermally-informed designs which recognize the impact of temperature on functional performance, to active thermal codesign which places functional paths and blocks in the most favorable locations on the chip, to fully-integrated codesign which deals with the impact of microfluidic channels and thermal interconnects on the electrical design and placement of electrical devices and cells and interactively balances the use of resources to optimize layout for energy consumption and functional performance.

  • Physics of failure models that address the failure mechanisms and reliability of the Gen-3 thermal management components, including erosion and corrosion in microchannels, microgaps, micropores, and microvalves; failure modes induced in the electrically active areas of the chip and/or substrate; and the impact of microfabrication and embedded cooling operation on the structural integrity and stress profile of the microchanneled substrate (intrachip) and/or the chip-to-chip bonding (interchip).

Bar-Cohen, A., and Bloschock, K., 2012, “Advanced Thermal Management Technologies for Defense Electronics,” Proceedings, SPIE Defense, Security and Sensing Conference, Baltimore, MD, April. [CrossRef]
Bar-Cohen, A., and Geisler, K. J. L., 2011, “Cooling the Electronic Brain,” Mech. Eng., 133(4), pp. 38–41.
Tuckerman, D. B., and Pease, R. F. W., 1981, “High-Performance Heat Sinking for VLSI,” IEEE Electron Device Lett., 2(5), pp. 126–129. [CrossRef]
Yarin, L. P., Mosyak, A., and Hetsroni, G., 2009, Fluid Flow, Heat Transfer, and Boiling in Micro-Channels, Springer, Berlin.
Bar-Cohen, A., Sheehan, J., and Rahim, E., 2012, “Two-Phase Thermal Transport in Microgap Channels-Theory, Experimental Results, and Predictive Relations,” Microgravity Sci. Technol., 24, pp. 1–15. [CrossRef]
Copyright © 2013 by ASME
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References

Bar-Cohen, A., and Bloschock, K., 2012, “Advanced Thermal Management Technologies for Defense Electronics,” Proceedings, SPIE Defense, Security and Sensing Conference, Baltimore, MD, April. [CrossRef]
Bar-Cohen, A., and Geisler, K. J. L., 2011, “Cooling the Electronic Brain,” Mech. Eng., 133(4), pp. 38–41.
Tuckerman, D. B., and Pease, R. F. W., 1981, “High-Performance Heat Sinking for VLSI,” IEEE Electron Device Lett., 2(5), pp. 126–129. [CrossRef]
Yarin, L. P., Mosyak, A., and Hetsroni, G., 2009, Fluid Flow, Heat Transfer, and Boiling in Micro-Channels, Springer, Berlin.
Bar-Cohen, A., Sheehan, J., and Rahim, E., 2012, “Two-Phase Thermal Transport in Microgap Channels-Theory, Experimental Results, and Predictive Relations,” Microgravity Sci. Technol., 24, pp. 1–15. [CrossRef]

Figures

Grahic Jump Location
Fig. 1

Schematic representation of the prevailing “remote cooling” thermal management paradigm

Grahic Jump Location
Fig. 2

A cross-sectional conceptual schematic of an embedded cooling, Gen-3 (ICECool) device

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