Hybrid Bonding for Ultra-High-Density Interconnect

Hybrid bonding is one major advancement of ultrahigh density interconnect technology for heterogeneous integration. The through silicon via (TSV) technology has made chip stacking successful by creating external interconnect capability at both sides of a chip. Hybrid bonding serves the interconnect between chips replacing microbumping methods at bond pad pitch smaller than 10 μm. These two challenging technologies are key contributors in three-dimensional (3D) integrated circuits or heterogeneous integration to enable chip stacking with shortened interconnect length for performance improvement and energy consumption reduction [1–77].

The wafer-to-wafer hybrid bonding for image sensor chip stacking is the first commercial application with continuous scaling to the ultrahigh-density interconnect [1–6]. Manufacturing limitations for technology nodes moving beyond 7 nm favor smaller dies for higher yield. Functional design also shows advantages with chip stacking for better performances. Chip partitioning followed by heterogeneous integration becomes the technology trend for advanced applications. Hybrid bonding is anticipated to take a key technology role [7–11]. The innovative ultrahigh density interchip interconnect was reported as a front-end wafer level chip stacking platform [7]. The hybrid bonding technology platform has been considered for various applications. 3D NAND chip stacking using hybrid bonding have been progressing in recent years [12]. The demand of high-performance computing (HPC) and artificial intelligence (AI) application continuously increases the requirements of bandwidth and memory capacity beyond the current capability. Alternative approaches using hybrid bonding methods for stacked 3D NAND, stacked DRAM, stacked embedded DRAM, or stacked high-capacity SRAM on a logic chip have demonstrated bandwidth and capacity increase and power consumption reduction [9–11,13–17]. The feasibility of pad pitch scaling to 0.4 μm has been demonstrated with heterogeneous integrated devices [13]. The limitations at sub-0.4 μm pitch scaling are currently under investigation [13,18–20].

A brief summary of the hybrid bonding methods was recently outlined by Lau [21]. In the scope of 3D heterogeneous integration with high precision, hybrid bonding is formed by both dielectric-to-dielectric and metal-to-metal bonding at the bonding interface. The simplified process eliminates copper pillar and underbump metal formation, underfill and solder tip dropping steps, and potential solder tip spreading from microbumping methods. The hybrid bonding using polymer interlayer cannot achieve high precision at bond pad pitch of microns or smaller. The challenges of hybrid bonding technology shifted to pad structure design, alignment or overlay accuracy, planarization by chemical mechanical polishing (CMP), control of copper dishing or protrusion, surface cleanliness and roughness, postbonding annealing temperature profiles, and copper grain microstructures are yet to be reviewed.

The benefits of die-to-wafer or die-to-die hybrid bonding are known to be more flexible than wafer-to-wafer bonding for integrating diverse known good dies together. In addition to the tradeoffs of precision and throughput, extending to die-to-wafer level, various challenges remain to be overcome toward goals at long-term roadmap horizon. Progresses have been observed in a few aspects such as innovative pad design to widen overlay tolerance [1,22–28], pad pitch scaling, collectively handling singulated dies for throughput improvement [23,24,29,30], pad design sensitivity assessment, and manufacturing capability improvement [3,31–37]. The industry standards to facilitate the implementation of chiplets heterogeneous integration are desired and anticipated [30,57]. This article reviews and analyzes these challenges and progresses. Bonding processes, defects, and microstructures issues would be addressed in separate articles [38–42].

There are a few most known manufacturing challenges for precision hybrid bonding processing technology. The precision includes flatness of the bonding surfaces, tight metal recess or protrusion, and minimal misalignment or overlay error. The postbonding annealing profiles determine the amount of metal expansion and metal diffusion to form good bonding. An exemplary schematic of hybrid bonding with copper metal pads is shown in Fig. 1. The well-aligned good bond pads formed by bonding during the postannealing process are shown in Fig. 1. When misalignment and defects occur, the copper bonding area would be smaller than that of designed pads as shown in Fig. 1. The mechanical and electrical connections would be affected. The crucial interfacial characteristics affected by copper–copper, dielectric–dielectric, and copper–dielectric bonded areas as shown in Fig. 2 should be properly optimized for desired performances, especially for submicron pad pitch.

The bonding schemes and innovative pad designs for improved process margins, different design concepts, and associated advantages and disadvantages are summarized and analyzed. The pad surface geometry affects the sensitivity to overlay tolerance, and the pad vertical structure is important to the copper dishing or protrusion variation. Without the solder tip on microbump to absorb the overlay error, pad design is a challenge and various designs have been experimented. Discussions on pad design are summarized in the subsequent section. Both protruded and recessed pads are considered in various pad structure designs.

Protruded pad has the characteristics of metal pad protruding from the dielectric surface with a step height. In principle, the bonding of top and bottom protruded pads treats the metal connection with priority.

A few pioneering works were conducted on pad surface preparation and bonding conditions to identify the challenges of bumpless interconnect [26,34]. CMP-Cu bonding by surface activated bonding (SAB) method was characterized by Shigetou et al. [34]. The bumpless copper electrodes at 3 μm diameter, 60 nm step height, and 10 μm pitch polished down to 0.5 nm root-mean-square (RMS) were proposed by Shigetou et al. for interchip bonding [26]. The self-designed flip-chip bonder with alignment precision of 1 μm could be performed under vacuum with Ar fast atom bombardment (Ar-FAB) cleaning to remove the copper surface oxide and perform bonding within 60 s. The vacuum of 3.5 10⁻³ Pa and pressure of 11 MPa on bond pad were determined experimentally.

Shigetou et al. experimented protruded bonding vias (PBV) of 3 μm and 4 μm diameters on top and bottom chips, respectively, at 6 μm pitch and 1.5 μm high with a step height over the dielectric surface around 60 nm, as shown in Fig. 3 [25]. Larger bottom pad was intended to widen the pad contact area margin. Using a similar bonding method in Ref. [26], without dielectric surrounding every Cu pad, a copper seal ring was added to the perimeter of the chip to prevent the gas leakage caused degradation. The copper bonding strength was tested to be 20 MPa and the Daisy chain of roughly 1,000,000 connections yielded reasonably [25].

The protruded copper vias or protruded copper pillar were investigated to form interconnect for die to wafer (D2W) by thermal compression bonding (TCB) by Sahoo et al. [43]. Without dielectric at the bonding interface, the protruded copper pillars were bonded to copper pads on the silicon interconnect fabric (Si-IF) or interposer wafers by two-stage TCB. The dies were first attached to the receiving wafer at 120 °C followed by postannealing at 300 °C or 400 °C for copper grain growth. The two-stage D2W-TCB bonding of copper pillar without constraints of dielectric gives more tolerance to surface particles and flatness. The copper pillar surfaces were in situ cleaned by formic acid vapor before die tacking. The separate die attachment and batch annealing could improve the throughput up to 300–1000 dies per hour. The electrical resistance and mechanical strength both demonstrated superior performances at 7 μm pitch. The process was similar to bumpless interconnect but simpler than that of hybrid bonding [43].

The early work of lock-and-key pad structure derived from a micro-electromechanical system application was tested on a 300-mm wafer by Liu et al. [27,44]. Protruded copper stud structures were formed after TSV reveal at the back side of the wafer. Recessed pad was formed at the receiving wafer as shown in Fig. 4. The two wafers were thermal compression bonded using a polyimide adhesive layer. The copper stud became compliant under thermal compression conditions to form bonded interconnect.

The pad structures were later simplified by removing the polyimide layer and generalized without association with TSV by Chen et al. into a pair of copper pads, one large recessed and one small protruded, as shown in Fig. 5(a) [28]. The part (b) is a schematic of protruded bonding via (PBV) structures described in Sec. 3.1.1 [25]. The misalignment design tolerance was defined as ½ (top pad dimension–bottom pad dimension). The misalignment was constrained for Lock-n-key structures while the PBV structures could allow more misalignment. The sensitivity of misalignment and interfacial voids on electrical performances was tested and discussed in the subsequent Sec. 4 [28].

Similar pad structures were proposed recently by adding a top SiCN dielectric cap layer to improve the bonding strength and named as Nail-to-pad (NTP) structures by Kim et al. [45] and Beyne et al. [22] as shown in Fig. 6. The copper exposed to oxide at the interface can therefore be shielded by the SiCN diffusion barrier. The bonding layer becomes the combination of dielectric layer and the dielectric cap layer embedding the copper via and the copper pad. Dissimilar dielectric cap layers were proposed by Kim et al. [46], and SiON cap layer was also considered [47] for the purposes of better bonding strength. The SiCN is consistent with the cap layer for back end of line (BEOL) copper dual damascene and is more popular.

The pad size differences were equivalent to two times of misalignment tolerance, Δ [22]. To improve the global topography, thicker oxide of 0.8 μm was deposited and polished back to 0.5 μm. The pad protrusion was limited to 5 nm while large pad recess target was minimal [45]. Pad structures of unequal sizes of 0.9 μm/2.7 μm and equal sizes of 0.18 μm/0.18 μm with 3.6 μm pad pitch and maximum allowable misalignment tolerance of 0.9 μm were tested. The bonding was performed by room temperature SAB inside multistage bonder with postanneal at 250 °C/2 h in furnace. Resistivity tests showed the 0.9 μm/2.7 μm pad structure outperform the 0.18 μm/0.18 μm structure with 96% yield at pad pitch of 3.6 μm. [45]. Scalability test on unequal pad structures is discussed in subsequent Sec. 5.

This hybrid wafer bonding method was introduced to production at pitch of 4 μm by Kagawa et al. [2]. Dual damascene process was conducted to form the pad-on-via (POV) bonding structure and the CMP process was optimized to ensure very flat surface with slightly sticking-out copper pad. The copper–copper bonding was formed by copper diffusion and the dielectric-dielectric bonding was formed by dehydration at postbonding annealing. The hybrid bonding passed the stress-induced voiding test [48].

Kagawa et al. presented the pad structure of a square copper pad on a copper via on BEOL metal layer with equal size on both chips to be bonded [1]. The pitch was 3 μm with copper pad of 1.5 μm square as shown in Fig. 7(a). The maximum misalignment tolerance or critical overlay tolerance, 1/2 pitch - critical spacing, of 0.5 μm was derived from the critical spacing between adjacent copper pads of 1 μm. The measured alignment precision was averaged at 0.2 μm ranging between 0.15 and 0.35 μm [1]. The critical spacing was considered conservative against the bonder precision. The resistance test and time-dependent-dielectric breakdown (TDDB) test both yielded reasonable results on 300 mm wafer. The converted lifetime using Black’s equation was 10 years [1].

Further scaling to 1 μm pitch with a square pad at 0.5 μm and pad spacing at 0.5 μm with modified pad-on-via structure shown in Fig. 7(b) was reported by Kagawa et al. [4]. The electrical tests demonstrated feasible misalignment tolerance stretchable up to 0.4 μm [4].

A recent work using protruded pads was reported by Fisher et al. [49]. In this work, the pattern sensitivity and bonding distortion concerns were addressed. Bonding structure was 2 μm square pad on via with pitch of 5.76 μm. A step height of 5–6 nm above dielectric surface prior to bonding was shown in an example in Fig. 8. The hybrid wafer bonding was conducted in vacuum chamber using plasma surface activation followed by room temperature SAB and postannealing. The alignment variation between wafer center and edge due to bonding wave was improved with the shape correction feature added. The encouraging results of the reduced misalignment at wafer edges were shown in Fig. 9. The pads were in uniform array with activated sites connected to vias from underlying layers. It reduced some pattern density related issues during CMP [49]. The contact resistance tests comparing pads misaligned at 1100 nm versus 30 nm resulted in 10–15% higher resistance for bigger misalignment. No voids were observed throughout the bonded wafer stack [49]. Reliability tests through 8 × 10⁶ via chains by JEDEC-style temperature cycle and high temperature storage tests showed passing results [49].

Recessed pads have the characteristics of metal pad recessed from dielectric surface with a dishing or recess depth prior to hybrid bonding. A few innovative pad design concepts are derived by recessed pad structures.

The patented direct bond interconnect (DBI) and associated exemplary recessed bond pad designs were presented by Gao et al. [23]. The DBI bonding process is a two-stage process by forming room temperature dielectric–dielectric bonding followed by a metal-metal connection by low temperature annealing at 150 °C–300 °C as shown in Fig. 10. The mechanisms are metal expansion more than dielectric during postbonding annealing, which brings the two metal surfaces together to form diffusion bonding [23]. The recess of metal is a crucial parameter.

One of the exemplary grid-to-pad design for 40 μm pad pitch with refined grid pads in one chip and distributed circular pads in another chip to be DBI bonded was shown in Fig. 11 to improve the process margin against misalignment [23]. The refined grid-type structure was in a redistribution layer with line-space pitch of 10 μm and the circular pad was 15 μm in diameter. The recess was pad size dependent, and the improvement of CMP process could help control the copper recess.

The die to wafer bonding preparation was achieved by de-ionized water clean and plasma activation. The wafer surface was protected by a coating before dicing. Singulated dies were collectively placed in a tray on aligned locations for coating removal and plasma activation followed by bonding to another fabricated wafer by a bonder. The bonder precision at 2.5 μm was acceptable with the special designed pad structures for die-to-wafer bonding. Continuous stacking was feasible for chip/wafers with dual side interconnection pads. A final annealing was conducted after all stacking was completed. Since the dielectric–dielectric bonding was formed surrounding the recessed metal pad, the annealing was performed in air. Reliability tests on temperature cycling and high temperature storage resulted in less than 10% resistance degradation passing the requirements of JEDEC standards [23].

A collective die-to-wafer hybrid bonding method was presented by Suhard et al. [24]. The singulated dies were collectively placed on 300 mm wafer with adhesive layer for cleaning and preparation then bonded to another 300 mm processed wafer for wafer-to-wafer level hybrid bonding. The innovative cross-lines pad design intended to relax the bonding precision tolerance for die-to-wafer bonding was shown in Fig. 12. The pad structures were in group of parallel line sectors. The control of line width could help to improve the CMP caused metal recess nonuniformity. These line sectors were protruded for 5 nm followed by etching to result in 5 nm recess. The receiving wafer had parallel line sectors perpendicular to those on incoming dies. The copper–copper interconnections were formed at the intersection of these cross lines at the interface as shown in Fig. 12.

The electrical resistance test with various pads and pitches as shown in Fig. 12 resulted in good yield in large pitch. The yield went down at 10 μm pitch to 50%. Various factors might have caused the low yield without an optimized process for small pitch with tight misalignment margin. Additional defects were concerns due to the additional protective coating, removals, and cleaning involved in handling singulated dies. The misalignment on the Besi placement tool at the time of experiment was calibrated to be centered on 2 μm with 1.5 μm achievable after optimization [24].

Pad-on-multiple via structures were designed to consider the impact of pitch shrinkage on interconnect robustness with various current densities at pad pitches ranging from 8 μm to 1.44 μm, as shown in Fig. 13, by Jourdon et al. [50]. The interconnect between top and bottom chips could be achieved at large bond pad pitch with redundant vias or small bond pad pitch with multiple small individual pad-on-via structures with different current densities. The wafer-to-wafer hybrid bonding was achieved by using standard EVG tool with alignment accuracy at 200 nm with postannealing at 400 °C with acceptable electrical results. The copper oxide at the pad surface was not considered significant due to the demixion effect during copper annealing. Electromigration tests and thermal cycling tests yielded equivalent results for large and small pad pitches. Although the current density ranged from minimum to maximum, the electromigration failure occurred not at hybrid bonding interface but at the BEOL layer connecting to bonding vias. The electrical resistance increased 8% when copper pad contact area reduced to 10% of pad area. However, in this design, the pad size was larger than via diameter [50].

A pad-on-via structure with high aspect ratio pad and short via for hybrid bonding interconnect was designed in a holistic view to optimize the current density and dielectric surface for ultraflatness as well as the impacts on the parasitic resistance, capacitance, and inductance for specific applications as shown in Fig. 14. The dielectric surface was specially treated to prevent particulate contaminates during dicing and handling singulated dies by Elsherbini et al. [35,36]. The pads were hexagonally populated. The die-to-wafer hybrid bonding for chiplets heterogeneous integration was performed by direct placement method [36]. The desirable industry consensus and industry standards for handling chiplets fabricated from different technology nodes and factories for heterogeneous integration were also voiced [36].

The unequal and equal high aspect ratio pad-on-via approaches also demonstrated acceptable performances at 400 nm pitch by Chew et al. [78]. Without lithographic pattern feature correction, square pad could result as circular pad and hexagonal array was more efficient.

An unequal pad design having tapered via, without specialized protrusion/recess pair, was adopted for 3D-NAND application as reported by Ouyang et al. [12]. The memory cells and CMOS periphery circuits were fabricated on two separate wafers with the bonding layers processed on BEOL layers with pad pitch at 1 μm and dielectric cap layers at the bonding surfaces as shown in Fig. 15. The bonded system achieved good reliability test results. Double cantilever beam test was performed and found only 5% fracture at the interface. Electromigration test also resulted in voids at BEOL layers not the hybrid bonded interface [12].

The recent report on bonding vias at pad pitch of 0.5 μm was shown in Fig. 16 [18]. The via critical dimension (CD) was 200 nm on both top and bottom wafers in Fig. 16(a) while the unequal vias CDs at top and bottom wafers were respectively 250 nm and 200 nm in Fig. 16(b). The SiCN was optimized for higher bonding energy and better diffusion barrier as reported by Ma et al. [18]. An investigation of pad pitch at 0.3 μm was conducted by Sherwood et al. using bonder overlay tolerance at 100 nm with the feasibility of hybrid bonding demonstrated [20].

Various pad structures and materials have been researched and examined by many researchers and industry players with the implied trends of pad structure designs. This review cannot include and detail all of them. The hybrid bonding technology has demonstrated scaling feasibility to sub-0.5 μm pitch with uniformly populated pads or vias [18,36]. To meet the diverse design requirements, a combination of populated pads and copper lines was enabled by the advanced CMP processes. The level of maturity of the hybrid bonding technology has been reported by Kagawa et al. in 2023 [3].

The performance of hybrid bonding has to meet the necessary requirements such as overlay tolerance, mechanical strength, and electrical and thermomechanical reliability. Most reliability tests described in Secs. 3.1.3, 3.2.1, and 3.2.5 showed passing results based on JEDEC standards. A few concerns are highlighted here. Analytical projection is desirable to reduce tedious experiments. The early work by Kim et al. in 2016 considered the voided areas surrounding the metal–metal and dielectric–dielectric bonding areas [45]. Recently, Lu in 2021 proposed a simple method to assess and analyze the projected hybrid bonding performance during design phase based on interfacial characteristics [51]. The assessment method calculated the projected metal–metal, dielectric–dielectric, and metal–dielectric bonding area percentages to reveal the sensitivity of pad design to overlay tolerance and other performances as shown in Fig. 2. Dimensions in exemplary cases were normalized by the respective pitch in each case. The normalized pitch was set to 1 μm for side-by-side comparisons with overlay tolerance ranging between 0.0 μm and 0.3 μm. The assessment could be extended to the performance comparisons of mechanical bonding strength, resistance, and thermos-mechanical performances associated with the CTE mismatch by metal pad pattern density and orientation between top and bottom pads [51].

Analysis based on the method proposed by Lu [51] but adding the fifth case with the 0.18 μm/0.72 μm pads at 0.9 μm pad pitch by NTP design and a sixth case with 3 μm/4 μm PBV at 6 μm pad pitch to Fig. 5 of Ref. [51] is summarized in Fig. 17. The first case of nail-to-pad (NTP1) was sizing the top pad to meet the overlay tolerance while the fifth case of nail-to-pad (NTP2) was fixing the nail size with the overlay tolerance of 0.3 μm. The terminologies of alignment, misalignment tolerance, and overlay accuracy or error were often used interchangeable in hybrid bonding. However, at the fine pitch range, the components of each overlay error were separated and well explained by Mitsuishi et al. [27,33]. The overlay accuracy is attributed by shift and rotation components caused by alignment stage and control system and distortion components, including scaling and residual, caused by wafer bonding wave at different temperature, air conditioning, correction system, and incoming wafers [27]. A typical distortion caused by wafer bonding wave could range from 0.5 μm to 1.5 μm of scaling component and 50 nm to 100 nm of residual component [33]. The improvement is aiming at 50 nm overlay accuracy [33]. Example of using shape correction feature was experimented by Fisher et al. shown in Fig. 9 of Sec. 3.1.3 [49].

The copper–copper bonding areas decrease with the increase of overlay error. The sensitivity to overlay accuracy is shown in Fig. 17. The POV and PBV designs appear to have moderate sensitivity, but PBV does not have dielectric–dielectric bonding. Equivalent pad designs of PBV with dielectric should achieve same projection. However, if the copper pattern density is constrained below 25%, the advantages of unequal pad are diminishing [78]. The cross-line and nail-to-pad (NTP2) with nail size fixed under 0.3 μm overlay tolerance appear to be insensitive to overlay error in the range of test, but the copper–copper bonding areas appear to be small. The simple method of evaluating interfacial characteristics demonstrates some ability to predict the sensitivity to overlay accuracy at design phase.

Interfacial characteristics are dependent on the materials and the annealing temperature profiles. For example, the bonding energy of copper–copper depends on the annealing temperature, microstructures of copper, and duration for grain growth to achieve strong bonding. Copper–copper bonding energy can range up to 25 J/m² for large scale bonding. However, the brittleness of copper might be increased at fine pad size due to the constraints from pad walls for limited plastic deformation. Low annealing temperature does not allow much diffusion and grain growth except on specially treated microstructures [75,77]. The bonding energy range for SiCN–SiCN is 1.4 J/m²–2.5 J/m² for annealing temperature from 200 °C to 250 °C [22,54]. Bonding energy of SiO₂–SiO₂ is typically at 2 J/m² and has been demonstrated to be sufficient to support the subsequent processing steps [22,54,55]. The SiCN–SiCN bonding was investigated by characterizing the dangling bond density postsurface activation. The dangling bond density was observed to reduce after postbonding annealing and contributed to formation of SiCN–SiCN bond. The SiCN has been commonly used between interconnect interlayer dielectric to reduce copper diffusion into oxide. The adoption of SiCN cap layer at bonding surface has been observed at fine pitch application as reported by Peng et al. [74]. The bonding energies of copper to SiO₂ and copper to TiN were surveyed [51] and found to be close to 1.02 J/m² [52] and 1.4 J/m² [53], respectively [51–53,55,56]. The bonding between copper and the dielectric material, either SiO₂ or SiCN, at the misaligned areas, is expected to be weaker. To achieve the equivalent 2 J/m² bonding energy, a hybrid bonding with a square pad size of ½ of pad pitch, the copper–copper bonding at zero and 1/6 pad pitch misalignment but full dielectric–dielectric delamination will require respective 8 J/m² and 18 J/m² copper–copper bonding energy to sustain the interfacial bonding for subsequent processing steps.

Surface energy for die level hybrid bonding was recently characterized by Sakuma et al. [54]. A single-beam cantilever test structure, modified from double cantilever beams by making the bottom beam immobile, was proposed for die level test with sample size 10 × 10 mm². The typical razor blade test is conducted with 1–2 inch of blade insertion for wafer-to-wafer bonding test. To ensure the fracture could occur at the desired die-to-wafer interface, the top sample thickness was selected to ensure the bending stiffness would not cause the unexpected fracture. The adhesion of epoxy to the sample and the silicon beam would be strong enough so the sample would not delaminate from the silicon supporting beam. The supporting beam was also longer than the sample to form precrack. The test sample consisted of 6 μm diameter uniformly distributed copper pad with 12 μm pad pitch. The fracture test on copper/SiCN hybrid bonding sample resulted in bonding energy in a range of 1.2–5.5 J/m². The associated fracture surface morphology of copper pads ranged from unbonded to strong bonding with ductile fracture surface were shown in Fig. 18. The results shared some implication of the effects of a strong copper–copper bonding to the interfacial energy of the hybrid bonding [54]. Summing the prorated bonding energy of all interfacial elements of each pad design gives some comparisons of mechanical strength. However, for fine pitch at sub-0.4 μm and below, additional concerns were observed with increased interfacial delamination. Copper density was a concern but required further investigation [20]. It is anticipated that the demands for precision at every step would be much more challenging at fine pitch of sub-0.4 μm and beyond.

The thermo-mechanical performances of pad structures can be compared likewise by the different copper volumes and pattern orientations between top and bottom pads. Asymmetric averaged CTEs across the interface is expected to result in higher thermo-mechanical stresses [51].

The sensitivity of hybrid bonding to electrical conduction can be reduced by design. A recent experimental study using a pad on a multiple-vias structure similar to Fig. 13(a) to characterize interfacial quality measured by contact resistance was reported by Jourdon et al. [57]. The specific contact resistivities obtained after a 400 °C bonding annealing by Kelvin resistors and Daisy chain extraction methods were, respectively, 1.20–1.70 × 10⁻⁹ Ω cm² and 2.25 × 10⁻¹⁰ Ω cm². The contact resistance measured by these test structures with multiple-vias was not affected much by voids or copper oxide nodules using cross Kelvin resistors and Daisy chain extractions. The test structure had via redundancy and the resistivity increase was mostly kept below 10% until void area ratio increases up to more than 90%. Electrical characterizations and simulations indicated that test structures became sensitive when the specific contact resistivity was higher than 10⁻⁸ Ω cm² since the highest current densities were located in BEOL copper line and bonding vias [57]. The advantages of these test structures are the characterization of the detailed misalignment magnitude and orientation using four bottom pads and one top pad for electrical connections. The electrical conductions at the four pads could detail the top pad positions for analysis and further improvement in many aspects as reported by Jani et al. [58].

The electrical tests using simple lock-n-key structures and oxide-recessed structures shown in Fig. 5 were performed to evaluate the effects of misalignment either by varying design tolerance with varying pad sizes or by fixed pad sizes with varying misalignment. Performance differences were detected and reported by Chen et al. as shown in Fig. 19 [28]. Protruded pad size decreased for higher design tolerance and the tested electrical resistances increased as shown in Fig. 19(a). For the fixed pad sizes but varying misalignments, the resistances did not change much until the misalignment exceeding the range of Lock-n-key design tolerance. At these extended ranges, the PBV showed resistances increased with misalignment as shown in Fig. 19(b).

A recent test on die to wafer bonding by direct placement method performed with coarse bonder alignment tolerance at 3 μm for 2 μm pad and 4 μm pad pitch found the daisy chain resistance increases with misalignment as reported by Workman et al. [59]. Fisher et al. also reported the sensitivity of misalignment on the contact resistance. The tests comparing pads misaligned at 1100 nm versus 30 nm resulted in 10–15% higher resistance by 1100 nm misalignment [49].

The electromigration failure locations were often identified at the BEOL layer connecting to bonding vias but not the interface of hybrid bonding pads as described in Sec. 3.2.5. The concerns of misalignment on electromigration performance on hybrid bonding wires were recently investigated by using copper wires at 0.7 μm line width and up to 0.15 m line length by Kagawa et al. [3]. The sheet resistance increased about 5% for 0.3 μm misalignment. The extrapolated electromigration lifetime resulted in 27 years at 0.3 μm misalignment versus 40 years without misalignment. The degradation was attributed to the copper–oxide bonding interface at misaligned area vulnerable to copper diffusion to cause void formation and dielectric breakdown [3].

The performances of hybrid bonding could be affected by many factors. One experiment conducted to eliminate the bonding pad after TSV reveal and thin down the dielectric cap layer for better thermal performance. The electrical resistance and thermal resistance were reduced with the tradeoff of increased parasitic capacitance. It resulted in negative net benefits. As a result, the performance co-optimization is desirable as reported by Kuo et al. [60]. Likewise, the processing elements and integration should also be co-optimized as discussed by Sherwood et al. [20]. Moreau et al. summarized many reliability concerns. However, the reliability performances reported by hybrid bonding implemented in commercial products were robust [61]. For extending to smaller pitches, research and development are still ongoing.

The performance assessed in Sec. 4 revealed the advantages and disadvantages of various pad designs. The scalability of hybrid bonding is constrained by the bonder capability, CMP process robustness, postannealing performance, etc. The current commonly used bonder has overlay accuracy around 200 nm @ 3 σ for wafer-to-wafer bonding and sub 2 μm for die-to-wafer bonding using collective dies methods [31]. Some ongoing improvement of bonder with overlay accuracy down to 50 nm is to be discussed in the subsequent Sec. 6.

A couple of POV structures adopted for commercial applications as shown in Fig. 7 are further analyzed. At pitch of 3 μm, the pad size, the diameter of the bonding via, and the critical spacing between adjacent pads were respective 1/2, 1/5, and 1/3 of the pitch as shown in Fig. 7(a). The parametric study on overlay tolerance was conducted over the pitch range from 0.6 μm to 6 μm as shown in Fig. 20(a). The red triangle marked the criteria of critical overlay tolerance, ½ pitch–critical spacing, determined by Kagawa et al. [1]. The black square marked the area at the bottom of the bonding via for current conduction. The critical spacing was likely constrained by processing variation, but the area of bonding via is the limiting factor for current conduction.

The recent POV pad design modification for fine pitch applications around 1 μm pitch was shown in Fig. 7(b). The pad size, the diameter of the bonding via, and the critical spacing between adjacent pads were respective 1/2, 2/5, and 1/8 of pitch [4]. The area at the bottom of the bonding via was marked by black square and the critical overlay tolerance was marked by red triangle as shown in Fig. 20(b). The electrical tests indicated the misalignment can be stretched to 0.4 μm at 1 μm pitch as reported by Kagawa et al. [4]. The current conduction might become sensitive to the overlay error with enlarged bonding vias.

Analysis on the scalability of unequal pad sizes by NTP structures was performed down to 0.72 μm pitch for wafer-to-wafer level bonding with the resistance test results shown in Fig. 21. A set of bonding pads are fabricated with SiCN dielectric cap layer. Bonding was conducted by bonder with precision limit at 250 nm, 250 °C postbonding annealing to strengthen SiCN-SiCN bonding, and 350 °C for copper–copper bonding. The 180 nm/540 nm pads with overlay tolerance of 180 nm yielded 50% as shown in Fig. 21 reported by Beyne et al. [22]. The yield is expected to be improved with bonder precision improvement. The main drawback of this method is the asymmetric properties across the interface.

The scalability of the unequal pad approach was further explored for the SRAM-on-logic applications at 3 nm and 2 nm technology nodes with hybrid bond pitch down to 700 nm as reported by Chen et al. [14]. For the critical application at fine pitch, the parasitic resistance and capacitance were concerned [14].

The other critical concern for the success of hybrid bonding at fine pitch is the amount of protrusion of the bonding pad associated with the spacing between pads and the copper pattern density of the recessed pads. The dielectric bending caused by protruded copper pad at sub-1 μm pitch increased chances of voids between pads as shown in Fig. 22. Likewise, some roll-off effect was observed with high pattern density of copper pads at CMP. Although a comfort zone of copper pattern density was constructed, upper bound of 25% was suggested for better yield as reported by Kim et al. [62]. The control of limited copper protrusion is very challenging. It becomes a critical question in managing limited copper protrusion or copper recess at sub-1 μm pitch and beyond.

For copper recess, the pad dimension was found crucial to the copper expansion during postbonding annealing to achieve good copper-copper contact. Jourdon et al. conducted finite element analysis on the amount of recess allowed to enable copper–copper bonding during the postanneal as shown in Fig. 23 [50]. Given the same copper recess, the interfacial copper–copper contact area increased with the pad sizes for higher available copper volume.

The simulation trends reported by Ji et al. are summarized and shown in Fig. 24 [63]. The finite element analysis was conducted on three designs to reveal the interfacial hybrid bonding area percentages after postannealing at 300 °C [63]. Designs A, B, and C consisted of bonding structures of respectively two bond pads, one bond pad and one TSV bond pad, and two TSV bond pads. The dishing could be bridged more efficiently for Design C with both TSV bond pads [63].

The additional concerns were raised by Ayoub et al. in 2022 for scaling to submicron pitch. The thermal expansion of single crystal grain is crystal orientation dependent. The copper grain orientation within the pad could cause expansion differences up to several nanometers and the recess criteria should be set by the grain crystal orientation with minimum expansion [64]. Nonetheless, the RC delay contributed by tight spacing between adjacent pads was also raised as a concern [64]. Adjusting the pad dimension for RC delay optimization was suggested at fine pitch [64]. Overall, performance gains were observed for hybrid bonding demonstrated at 0.4 μm pitch after necessary optimization as reported by Chia et al. [13].

The wafer-level hybrid bonding process has been implemented in commercial products. Enquist et al. in 2009 indicated that the hybrid bonding technology is a low cost of ownership method comparing against microbumping method [72]. However, hybrid bonding requires different processing and equipment sets. For example, multichamber equipment is required to manage the surface activation and bonding processes as described by Fujino et al. [65]. In the aspect of technology requirements, hybrid bonding demonstrates its capability at sub-0.5 μm pitch beyond the capability of microbumping.

The scaling of hybrid bonding is challenged by overlay accuracy. These issues are currently under investigation by added industry players from front-end process equipment suppliers specialized in lithography overlay precision into this field with encouraging results presented by Mitsuishi et al. [33,37]. 40-nm overlay accuracy at 95 percentile was achieved. The shift and rotation precision can be improved inside of the bonder while the distortion components caused by the wafer saddle formation to form wafer to wafer contact might require lithographic correction outside of the bonder [37]. The ongoing bonder improvement to reduce the overlay error to 50 nm for wafer-to-wafer bonding might support the pitch scaling down to 200 nm–500 nm range [33].

Recent tests of wafer-to-wafer hybrid bonding performed at 0.5 μm pitch and 0.25 μm pad at wafer-to-wafer level, the overlay accuracy was demonstrated within 60 nm as reported by Netzband et al. [19]. Some investigation extended to 0.4 μm pitch and demonstrated feasibility for wafer-to-wafer level hybrid bonding by Chia et al. [13] with further studies at 0.3 μm pitch by Sherwood et al. [20].

Extending the technology to die-to-wafer hybrid bonding, a few manufacturing issues of throughput, die protection during dicing, cleaning, and singulated die handling have been under investigation.

The preservation of surface cleanliness and integrity through the dicing process is a challenge. Sacrificial layers were coated on both front and back side of memory wafer prior to dicing by Chen et al. [17]. Using protective coating at die singulation and cleaning showed better results by Fan et al. [66]. Process flow of cleaning and plasma activating singulated dies followed by high precision pick-and-place to direct die-to-wafer bonding was reported by Uhrmann et al. [40]. The distortion components of overlay accuracy within each die with center and edge differences were reported by Mirkarimi et al. [68]. Additional challenges beyond overlay accuracy were also found for multiple-die stacking [69]. The die-to-wafer bonder using two bond heads to reduce the delay time caused by die handling and pick-and-place improved the throughput to greater than 2000 unit per hour (UPH) as reported by Brandstatter et al. [32].

Collective die-to-wafer bonding adopts the concept of reconstructing wafer with known-good-dies under high-throughput coarse alignment. Different approaches have been explored such as populating dies in a tray or on a carrier with organic adhesive tapes [23,24]. In the example performed by Suhard et al., the top wafer was protective coated and followed by the typical process of backside grinding, transferred to dicing tape, and diced [24]. These known good dies were pick-and-place on an Si carrier with adhesive tape as shown in Fig. 25. The adhesive between dies is removed followed by removing the protective coating as shown in Fig. 25. The collective die-on-wafer and the receiving wafer were then surface activated and bonded at 13 KN, 250 °C, 30 min on SiCN–SiCN dielectric surface. The carrier wafer was then removed. The bonded dies on the receiving wafer were annealed at 350 °C for 2 h to connect the copper structures from the dies to the copper structures from the receiving wafer by copper pumping [24,76].

A recent report of collective die-to-wafer bonding or reconstructed die-to-wafer bonding proposed to use dielectric film as temporary bonding layer by Inovue et al. [70]. Chips or dies were pick-and-placed on the carrier wafer coated with thin oxide dielectric film with weak bonding. The advantage of using dielectric film is the less amount of die shift [70]. Overall, the multiple advantages and disadvantages were addressed by Uhrmann et al. [67].

Capillary self-assembly method was investigated for reconstructing wafer with known good dies to improve die placement throughput [29,30,73]. Fukushima et al. proposed to utilize the surface tension of liquid droplet for capillary self-assembly [73]. This approach requires patterning the receiving areas to be hydrophilic with hydrophobic edges. The liquid droplet keeps the chip suspended on the receiving areas and the surface tension of liquid at the chip edges align chips by minimizing the total perimeter surface tension [73]. The recent work by Bond et al. experimented the effects of shape and aspect ratio of chips using water droplet, surface tension of 72.1 mN/m, and resulted some good chip alignment at 1 μm accuracy as shown in Fig. 26 [30]. The prototype equipment design is hopefully to be expanded to manufacturing level for assembling multiple dies on a wafer with throughput improvement [30]. Further process improvements in step heights and copper pad integrity were reported by Bourjot et al. [71].

The hybrid bonding technologies are briefly reviewed in this article, including bonding methods and various hybrid bonding pad structure designs. The challenges, crucial factors affecting performances, assessment and characterization methods, scalability, and manufacturing equipment improvement progresses are addressed. Feasibility of hybrid bonding has been demonstrated for heterogeneous integration at pitch down to 0.4 μm at wafer-to-wafer bonding level with further improvement in progress. The additional challenges and various approaches in die-to-wafer hybrid bonding are also highlighted with further improvement in progress. To extend these technologies to industry wide applications, the demands of manufacturing equipment improvement and industry standards for the preparation of sourcing dies or wafers processed by different technology nodes from different factories to the receiving sites for fabricating heterogeneous integrated chip-stacking, packages, and systems are also voiced.

The author is thankful to those who inspired and supported this work.

The datasets generated and supporting the findings of this article are obtainable from the corresponding author upon reasonable request.