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Journal Articles

Hybrid Bonding for Ultra-High-Density Interconnect

Mei-Chien Lu
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Review Articles
J. Electron. Packag. September 2024, 146(3): 030802.
Paper No: EP-23-1064
https://doi.org/10.1115/1.4064750
Published Online: March 8, 2024
View Article titled, Hybrid Bonding for Ultra-High-Density Interconnect
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Topics: Bonding, Semiconductor wafers, Copper, Overlays (Materials engineering), Design
Journal Articles

High Gain and Wideband Antenna-in-Package Solution Using Fan-Out Technology

Xuesong Zhang, Qian Wang, Chenhui Xia, Chaojie Zhou, Gang Wang, Jian Cai
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. September 2023, 145(3): 031009.
Paper No: EP-22-1039
https://doi.org/10.1115/1.4056991
Published Online: March 20, 2023
View Article titled, High Gain and Wideband Antenna-in-Package Solution Using Fan-Out Technology
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Topics: Design, Dipoles (Electromagnetism), Manufacturing, Millimeter waves, Packaging, Radiation (Physics), Signals, Simulation, Warping, Waveguides
Journal Articles

Viscoelastic Influence on the Board Level Assessment of Wafer Level Packages Under Drop Impact and Under Thermal Cycling

Abel Misrak, Rabin Bhandari, Dereje Agonafer
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. March 2023, 145(1): 011204.
Paper No: EP-21-1110
https://doi.org/10.1115/1.4054784
Published Online: August 3, 2022
View Article titled, Viscoelastic Influence on the Board Level Assessment of Wafer Level Packages Under Drop Impact and Under Thermal Cycling
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Topics: Glass transition, Reliability, Semiconductor wafers, Storage, Stress, Temperature, Testing, Viscoelasticity, Solders, Failure
Journal Articles

A Hybrid Antenna in Package Solution Using FOWLP Technology

Xuesong Zhang, Qian Wang, Bo Wang, Gang Wang, Xin Gu, Yu Chen, Lin Tan, Shengjuan Zhou, Jian Cai
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. September 2022, 144(3): 031005.
Paper No: EP-21-1024
https://doi.org/10.1115/1.4051379
Published Online: September 15, 2021
View Article titled, A Hybrid Antenna in Package Solution Using FOWLP Technology
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Topics: Design, Manufacturing, Millimeter waves, Semiconductor wafers, Warping, Waveguides, Solders, Temperature, Molding
Journal Articles

Fabrication Steps and Thermal Modeling of Three-Dimensional Asynchronous Field Programmable Gate Array (3D-AFPGA) With Through Silicon Via and Copper Pillar Bonding Approach

Leila Choobineh, Robert Carrol, Carlos Gutierrez, Robert Geer
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. September 2020, 142(3): 031106.
Paper No: EP-19-1098
https://doi.org/10.1115/1.4046848
Published Online: April 24, 2020
View Article titled, Fabrication Steps and Thermal Modeling of Three-Dimensional Asynchronous Field Programmable Gate Array (3D-AFPGA) With Through Silicon Via and Copper Pillar Bonding Approach
Open the PDF for Fabrication Steps and Thermal Modeling of Three-Dimensional Asynchronous Field Programmable Gate Array (3D-AFPGA) With Through Silicon Via and Copper Pillar Bonding Approach in another window
Topics: Bonding, Columns (Structural), Copper, Design, Gates (Closures), Manufacturing, Modeling, Semiconductor wafers, Silicon, Tiles
Journal Articles

Fatigue Prediction for Molded Wafer-Level Package During Temperature Cycling

Wan-Chun Chuang, Wei-Long Chen
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. March 2020, 142(1): 011007.
Paper No: EP-19-1042
https://doi.org/10.1115/1.4044489
Published Online: October 10, 2019
View Article titled, Fatigue Prediction for Molded Wafer-Level Package During Temperature Cycling
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Topics: Cycles, Fatigue life, Semiconductor wafers, Simulation models, Solders, Stress, Temperature, Creep, Assembly lines, Simulation results
Journal Articles

Warpage Characterization of Molded Wafer for Fan-Out Wafer-Level Packaging

Hsien-Chie Cheng, Yan-Cheng Liu
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. March 2020, 142(1): 011004.
Paper No: EP-19-1023
https://doi.org/10.1115/1.4044625
Published Online: September 19, 2019
View Article titled, Warpage Characterization of Molded Wafer for Fan-Out Wafer-Level Packaging
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Topics: Semiconductor wafers, Shrinkage (Materials), Temperature, Warping, Molding, Manufacturing, Epoxy resins, Packaging, Epoxy adhesives
Journal Articles

Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging

John H. Lau
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Review Articles
J. Electron. Packag. December 2019, 141(4): 040801.
Paper No: EP-18-1088
https://doi.org/10.1115/1.4043341
Published Online: May 17, 2019
View Article titled, Recent Advances and Trends in Fan-Out Wafer/Panel-Level Packaging
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Topics: Packaging, Semiconductor wafers, Solders, Warping, Etching
Journal Articles

Edge Trimming Induced Defects on Direct Bonded Wafers

Fumihiro Inoue, Anne Jourdain, Lan Peng, Alain Phommahaxay, Daisuke Kosemura, Ingrid De Wolf, Kenneth June Rebibis, Andy Miller, Erik Sleeckx, Eric Beyne
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. September 2018, 140(3): 031004.
Paper No: EP-17-1127
https://doi.org/10.1115/1.4040002
Published Online: May 11, 2018
View Article titled, Edge Trimming Induced Defects on Direct Bonded Wafers
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Topics: Damage, Grinding, Semiconductor wafers, Stress, Bonding
Journal Articles

Special Section on InterPACK 2017—Part 2

Kaushik Mysore, Sreekant Narumanchi, Ercan Dede, Reza Khiabani
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Guest Editorial
J. Electron. Packag. June 2018, 140(2): 020301.
Paper No: EP-18-1012
https://doi.org/10.1115/1.4039963
Published Online: May 9, 2018
View Article titled, Special Section on InterPACK 2017—Part 2
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Topics: Batteries, Density, Electronic packaging, Microelectromechanical systems, Optoelectronic devices, Packaging, Semiconductor wafers, Sensors, Reliability
Journal Articles

Improvement of Thermo-Mechanical Reliability of Wafer-Level Chip Scale Packaging

Lei Shi, Lin Chen, David Wei Zhang, Evan Liu, Qiang Liu, Ching-I Chen
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. March 2018, 140(1): 011002.
Paper No: EP-17-1035
https://doi.org/10.1115/1.4038245
Published Online: March 2, 2018
View Article titled, Improvement of Thermo-Mechanical Reliability of Wafer-Level Chip Scale Packaging
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Topics: Density, Design, Finite element model, Packaging, Reliability, Semiconductor wafers, Solder joints, Solders, Stress, Fatigue life
Journal Articles

Special Section on IMECE 2016

Justin A. Weibel, S. Ravi Annapragada
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Guest Editorial
J. Electron. Packag. June 2017, 139(2): 020301.
Paper No: EP-17-1032
https://doi.org/10.1115/1.4036627
Published Online: June 12, 2017
View Article titled, Special Section on IMECE 2016
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Topics: Failure analysis, Flexible electronics, Packaging, Reliability, Semiconductor wafers, Solders, Thermal analysis, Electronic packaging
Journal Articles

Characterization and Benchmarking of the Low Intertier Thermal Resistance of Three-Dimensional Hybrid Cu/Dielectric Wafer-to-Wafer Bonding

Herman Oprins, Vladimir Cherman, Tomas Webers, Abdellah Salahouelhadj, Soon-Wook Kim, Lan Peng, Geert Van der Plas, Eric Beyne
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. March 2017, 139(1): 011008.
Paper No: EP-16-1096
https://doi.org/10.1115/1.4035597
Published Online: January 10, 2017
View Article titled, Characterization and Benchmarking of the Low Intertier Thermal Resistance of Three-Dimensional Hybrid Cu/Dielectric Wafer-to-Wafer Bonding
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Topics: Bonding, Semiconductor wafers, Thermal resistance, Transients (Dynamics), Temperature, Steady state
Journal Articles

Recent Advances and New Trends in Flip Chip Technology

John H. Lau
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Review Articles
J. Electron. Packag. September 2016, 138(3): 030802.
Paper No: EP-16-1052
https://doi.org/10.1115/1.4034037
Published Online: July 25, 2016
View Article titled, Recent Advances and New Trends in Flip Chip Technology
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Topics: Bonding, Flip-chip, Flip-chip assemblies, Flip-chip devices, Manufacturing, Semiconductor wafers, Solders, Columns (Structural), Silicon, Packaging
Journal Articles

Size-Compatible, Polymer-Based Air-Gap Formation Processes, and Polymer Residue Analysis for Wafer-Level MEMS Packaging Applications

Erdal Uzunlar, Paul A. Kohl
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. December 2015, 137(4): 041001.
Paper No: EP-14-1114
https://doi.org/10.1115/1.4030952
Published Online: July 23, 2015
View Article titled, Size-Compatible, Polymer-Based Air-Gap Formation Processes, and Polymer Residue Analysis for Wafer-Level MEMS Packaging Applications
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Topics: MEMS packaging, Microelectromechanical systems, Polymers, Temperature, Semiconductor wafers, Reactive-ion etching, Nuclear magnetic resonance, Hardening (Curing)
Journal Articles

Reliability Assessment of Wafer Level Packages With Novel FeNi Under Bump Metallization

Jia Xi, Xinduo Zhai, Jun Wang, Donglun Yang, Mao Ru, Fei Xiao, Li Zhang, Chi Ming Lai
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. September 2015, 137(3): 031016.
Paper No: EP-15-1016
https://doi.org/10.1115/1.4030974
Published Online: July 21, 2015
View Article titled, Reliability Assessment of Wafer Level Packages With Novel FeNi Under Bump Metallization
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Topics: Ferronickel, Finite element analysis, Reliability, Semiconductor wafers, Solders, Temperature, Fracture (Materials), Failure mechanisms, Alloys, Stress
Journal Articles

Overview and Outlook of Three-Dimensional Integrated Circuit Packaging, Three-Dimensional Si Integration, and Three-Dimensional Integrated Circuit Integration

John H. Lau
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Review Articles
J. Electron. Packag. December 2014, 136(4): 040801.
Paper No: EP-14-1068
https://doi.org/10.1115/1.4028629
Published Online: October 15, 2014
View Article titled, Overview and Outlook of Three-Dimensional Integrated Circuit Packaging, Three-Dimensional Si Integration, and Three-Dimensional Integrated Circuit Integration
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Topics: Integrated circuit packaging, Manufacturing, Semiconductor wafers, Supply chains, Wire bonding, Packaging, Integrated circuits, Bonding
Journal Articles

Advances in the Fabrication Processes and Applications of Wafer Level Packaging

Peisheng Liu, Jinlan Wang, Liangyu Tong, Yujuan Tao
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Technology Review
J. Electron. Packag. June 2014, 136(2): 024002.
Paper No: EP-14-1006
https://doi.org/10.1115/1.4027397
Published Online: April 29, 2014
View Article titled, Advances in the Fabrication Processes and Applications of Wafer Level Packaging
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Topics: Manufacturing, Packaging, Reliability, Semiconductor wafers, Microelectromechanical systems, Solders, Solder joints, Copper, Polymers
Journal Articles

Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art

Dapeng Liu, Seungbae Park
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Technology Review
J. Electron. Packag. March 2014, 136(1): 014001.
Paper No: EP-13-1038
https://doi.org/10.1115/1.4026615
Published Online: February 18, 2014
View Article titled, Three-Dimensional and 2.5 Dimensional Interconnection Technology: State of the Art
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Topics: Bonding, Manufacturing, Semiconductor wafers, Solders, Packaging, Low temperature
Journal Articles

Investigation of Dual Electrical Paths for Off-Chip Compliant Interconnects

Raphael Okereke, Karan Kacker, Suresh K. Sitaraman
Journal: Journal of Electronic Packaging
Publisher: ASME
Article Type: Research-Article
J. Electron. Packag. September 2013, 135(3): 031004.
Paper No: EP-12-1102
https://doi.org/10.1115/1.4024112
Published Online: June 4, 2013
View Article titled, Investigation of Dual Electrical Paths for Off-Chip Compliant Interconnects
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Topics: Manufacturing, Reliability, Stress, Thermomechanics, Displacement, Semiconductor wafers, Copper, Simulation, Solders