Abstract

The International Roadmap for Devices and Systems shows Fin field-effect transistor (FET) array transistors as the mainstream structure for logic devices. Traditional methods of Fourier heat transfer analysis that are typical of Technology computer-aided design (tcad) software are invalid at the length and time scales associated with these devices. Traditional models for phonon transport modeling have not demonstrated the ability to accurately model three dimensional (3-d), transient transistor thermal responses. An engineering design tool is needed to accurately predict the thermal response of FinFET transistor arrays. The statistical phonon transport model (SPTM) was applied in a 3-d, transient manner to predict nonequilibrium phonon transport in an silicon-on-insulator (SOI)-FinFET array transistor with a 60 nm long fin and a 20 nm channel length. A heat generation profile from electron–phonon scattering was applied in a transient manner to model switching. Simulation results indicated an excess build-up of up to 17% optical phonons giving rise to transient local temperature hot spots of 37 K in the drain region. The local build-up of excess optical phonons in the drain region has implications on performance and reliability. The SPTM is a valid engineering design tool for evaluating the thermal performance of emergent proposed FinFET transistor designs. The phonon fidelity of the SPTM is greater than Monte Carlo and the Boltzmann Transport Equation and the length scale and time scale fidelity of the SPTM is better than direct atomic simulation.

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